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19-2846; Rev 1; 7/03
Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
General Description
The MAX9377/MAX9378 are fully differential, highspeed, low-jitter anything-to-LVPECL and anything-toLVDS translators, respectively, with a selectable divide-by-four function. Low propagation delay and high speed make them ideal for various high-speed network routing and backplane applications at speeds up to 2GHz in nondivide mode. The MAX9377/MAX9378 accept any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling standards. The MAX9377 outputs are LVPECL and have sufficient current to drive 50 transmission lines. The MAX9378 outputs are LVDS and conform to the ANSI EIA/TIA-644 LVDS standard. The MAX9377/MAX9378 are available in 8-pin MAX packages and operate from a single +3.3V supply over the -40C to +85C temperature range.
Features
o Guaranteed 2GHz Switching Frequency o Accept LVDS/LVPECL/Anything Inputs o Pin-Selectable Divide-by-Four Function o 421ps (typ) Propagation Delays (MAX9377) o 30ps (max) Pulse Skew o 2psRMS (max) Random Jitter o Minimum 100mV Differential Input to Guarantee AC Specifications o Temperature-Compensated LVPECL Output o +3.0V to +3.6V Power-Supply Operating Range o ESD Protection: >2kV Human Body Model (HBM)
MAX9377/MAX9378
Applications
Backplane Logic Standard Translation LAN WAN DSLAM DLC
PART MAX9377EUA MAX9378EUA
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 MAX 8 MAX
Pin Configuration
TOP VIEW
RST SEL IN IN 1 2 3 8 7 6 VCC LVDS/ANY OUT OUT RST
Functional Diagram
SEL /4
LVPECL (MAX9377) OR LVDS (MAX9378)
GND 4
MAX9377 MAX9378
5
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four MAX9377/MAX9378
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V Inputs (IN, IN, RST, SEL) ............................-0.3V to (VCC + 0.3V) IN to IN................................................................................3.0V Short-Circuit Duration (MAX9378 OUT, OUT) ............Continuous Continuous Output Current .................................................50mA Surge Output Current .......................................................100mA Continuous Power Dissipation (TA = +70C) 8-MAX (derate 5.9mW/C above +70C) ...............470.6mW JA in Still Air...........................................................+170C/W Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (IN, IN, OUT, OUT) ..............................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
LVCMOS/LVTTL INPUTS (RST, SEL) Input High Voltage Input Low Voltage Input High Current Input Low Current Differential Input Threshold Input Current Input CommonMode Voltage VIH VIL IIH IIL VIN = VCC or 2V VIL = 0 or 0.8V 2.0 GND 0 -20 VCC 0.8 150 +20 2.0 GND 0 -20 VCC 0.8 150 +20 2.0 GND 0 -20 VCC 0.8 150 +20 V V A A
DIFFERENTIAL INPUTS (IN, IN) VTHD IIN, I IN VCM VIN, V IN = VCC or 0V Figure 1 -100 -20 0.05 6 +100 +20 VCC 0.05 -100 -20 0.05 6 +100 +20 VCC 0.05 -100 -20 0.05 6 +100 +20 VCC 0.05 mV A V
LVPECL OUTPUTS (OUT, OUT) (MAX9377) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage VOH Figure 3 VCC 1.085 VCC 1.033 VCC - VCC - VCC 0.880 1.025 0.992 VCC0.880 VCC - VCC 1.025 0.978 VCC 0.880 V
VOL VOH VOL
Figure 3
VCC 1.830 595
VCC 1.755 725
VCC - VCC - VCC 1.620 1.810 1.717 595 725
VCC 1.620
VCC - VCC 1.810 1.699 595 725
VCC 1.620
V
Figure 3
mV
LVDS OUTPUTS (OUT, OUT) (MAX9378) Differential Output Voltage VOD Figure 2 250 370 450 250 363 450 250 348 450 mV
2
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Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER Change in Magnitude of VOD Between Complementary Output States Offset CommonMode Voltage Change in Magnitude of VOS Between Complementary Output States Output ShortCircuit Current, Either Output Shorted to GND Output ShortCircuit Current, Outputs Shorted Together POWER SUPPLY MAX9377, all pins open except VCC, GND Supply Current ICC MAX9378, RL = 100, quiescent, inputs are open 18.0 30 20 30 22 30 13 22 15 22 17 22 mA SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
MAX9377/MAX9378
VOD
Figure 2
1.0
20
1.0
20
1.0
20
mV
VOS
Figure 2
1.125
1.375 1.125 1.250
1.375
1.125
1.375
V
VOS
Figure 2
0.1
20
0.1
20
0.1
20
mV
IOS
VID = 100mV, one output GND, other output open or shorted to GND VID = 100mV, VOUT = V OUT
19.0
24
19.0
24
19.0
24
mA
IOSAB
4.0
12
4.0
12
4.0
12
mA
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Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four MAX9377/MAX9378
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency 1.34GHz, differential input transition time = 125ps (20% to 80%), input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V) MAX9377, LVDS outputs terminated with RL = 100 1% (MAX9378), TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 4)
PARAMETER Reset-to-Differential Output Low Delay Reset-to-Input Clock Setup Time Clock-to-Divider Output Propagation Delay SEL to Switched Output Delay MAX9377 Switching Frequency Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLH -tPHL| Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (20% to 80%) Added Random Jitter MAX9378 Switching Frequency Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLH - tPHL| Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (20% to 80%) Added Random Jitter fMAX tPLH tPHL tSKEW tR tF tRJ VOD 250mV Figure 3, SEL = 0 Figure 3, SEL = 0 Figure 3 (Note 6) Figure 2 Figure 2 fIN = 1.34GHz (Note 7), SEL = 0 2.0 250 250 2.5 363 367 3 93 93 0.8 600 600 30 220 220 2 GHz ps ps ps ps ps ps(RMS) fMAX tPLH tPHL tSKEW tR tF tRJ VOH - VOL 250mV Figure 3, SEL = 0 Figure 3, SEL = 0 (Note 6) Figure 3 Figure 3 fIN = 1.34GHz (Note 7), SEL = 0 2.0 250 250 2.5 421 421 6 116 116 0.7 600 600 30 220 220 2 GHz ps ps ps ps ps ps(RMS) SYMBOL tDR tSET tPCO tSEL Figure 4 Figure 4 Figure 4 (Note 5) Figure 5 0.5 0.6 0.3 1.0 0.6 CONDITIONS MIN TYP 0.8 MAX 1.0 UNITS ns ns ns ns
Note 1: Measurements are made with the device in thermal equilibrium. All voltages are referenced to ground except VTHD, VID, VOD, and VOD. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25C and guaranteed by design and characterization over the full operating temperature range. Note 4: Guaranteed by design and characterization, not production tested. Limits are set at 6 sigma. Note 5: tPCO is the delay associated with the frequency-divider function. The total delay when divide-by-four is selected is tPCO + tPLH. Note 6: tSKEW is the magnitude difference of differential propagation delays for the same output under same conditions; tSKEW = |tPHL - tPLH|. Note 7: Device jitter added to the input signal.
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Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
Typical Operating Characteristics
(VCC = +3.3V, differential input voltage |VID| = 0.2V, VCM = 1.2V, input frequency = 500MHz, outputs terminated with 50 1% to VCC - 2.0V (MAX9377), outputs terminated with 100 1% (MAX9378), TA = +25C, unless otherwise noted.)
PROPAGATION DELAY vs. TEMPERATURE
MAX9377/78 toc02
MAX9377/MAX9378
SUPPLY CURRENT vs. FREQUENCY
MAX9377/78 toc01
OUTPUT AMPLITUDE vs. FREQUENCY
900 800 OUTPUT AMPLITUDE (mV) MAX9377 700 600 500 400 300 MAX9378 500 480 PROPAGATION DELAY (ps) 460 440 420 400 380 360 340 320
MAX9377 NO LOAD 40 SUPPLY CURRENT (mA)
tPLH (MAX9377)
tPHL (MAX9377)
30
MAX9378 MAX9377
tPLH (MAX9378)
20
10
tPHL (MAX9378)
0 0 500 1000 FREQUENCY (MHz) 1500 2000
300 0 500 1000 FREQUENCY (MHz) 1500 2000 -40 -15 10 35 60 85 TEMPERATURE (C)
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9377/78 toc04
140 130 OUTPUT RISE/FALL TIME (ps) 120 110 tR (MAX9377) 100 90 80 70 -40 -15 10 35 60 tR (MAX9378) tF (MAX9378) tF (MAX9377)
85
TEMPERATURE (C)
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MAX9377/78 toc03
50
5
Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four MAX9377/MAX9378
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME SEL IN IN GND RST OUT OUT VCC FUNCTION Frequency Divider Select Input. High = divide by four, low = no division. Internal 75k pulldown to GND. Differential LVDS/Any Noninverting Input Differential LVDS/Any Inverting Input Ground Frequency Divider Reset Input. Active high, asynchronous, reset. Internal 75k pulldown to GND. MAX9377 MAX9378 MAX9377 MAX9378 Differential LVPECL Inverting Output. Terminate with 50 1% to VCC - 2V. Inverting LVDS Output. Terminate to OUT with 100 1%. Differential LVPECL Noninverting Output. Terminate with 50 1% to VCC - 2V. Noninverting LVDS Output. Terminate to OUT with 100 1%.
Positive Supply. Bypass from VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device
Detailed Description
The MAX9377/MAX9378 are fully differential, highspeed, low-jitter anything-to-LVPECL and anything-toLVDS translators, respectively, with a selectable divide-by-four function. Low propagation delay and high speed make them ideal for various high-speed network routing and backplane applications at speeds up to 2GHz in nondivide mode. The MAX9377/MAX9378 accept any differential input signals within the supply rails and with a minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling standards. The MAX9377 outputs are LVPECL and have sufficient current to drive 50 transmission lines. The MAX9378 outputs are LVDS and conform to the ANSI EIA/TIA-644 LVDS standard.
Table 1. SEL AND RST Truth Table
RST X H L SEL L or open H H OUTPUT No frequency division. Outputs are placed in differential low. Divide-by-four function.
high when powering up the device with SEL high prevents the unknown states with the divider from being propagated to the outputs. If the device is powered up with SEL high but without asserting RST, the outputs are only guaranteed to be 1/4th the input frequency after 2.5 cycles have been applied to the input.
LVPECL Outputs (MAX9377)
The MAX9377 LVPECL outputs are emitter followers that require external resistive paths to a voltage source (VT = VCC - 2.0V typ) more negative than worst-case VOL for proper static and dynamic operation. When properly terminated, the outputs generate steady-state voltage levels, VOL or VOH with fast transition edges between state levels. Output current always flows into the termination during proper operation.
Inputs
Inputs have a wide common-mode range of 0.05V to (VCC - 0.05V), which accommodates any differential signals within the supply rails, and requires a minimum of 100mV to switch the outputs. This allows the MAX9377/MAX9378 inputs to support virtually any differential signaling standard.
LVDS Outputs (MAX9378)
The MAX9378 LVDS outputs require a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor. With a 3.5mA typical output current, the MAX9378 produces an output voltage of 350mV when driving a 100 load.
RST and SEL Inputs
The frequency-divide functions are controlled by two LVCMOS/LVTTL inputs, RST and SEL. SEL selects either the divide-by-four function or a no-division function as shown in Table 1. RST, an asynchronous activehigh input, resets the divide-by-four within the device and places the circuits into a known state. Setting RST
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Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four MAX9377/MAX9378
OUT VCC DRV OUT VOD RL / 2 VID VCM (MAX) = VCC - 0.05V CL CL GND VOD(+) 80% VID VCM (MIN) = 0.05V 0V GND OUT - OUT tR tF VOD(-) 80% VOS RL / 2
20%
20%
Figure 1. Differential Input Definition
Figure 2. LVDS Output Load and Transition Times
Applications Information
IN
LVPECL Output Termination (MAX9377)
Terminate the MAX9377 LVPECL outputs with 50 to (VCC - 2V) or use equivalent Thevenin terminations. Terminate OUT and OUT with identical termination on each for low output distortion. When a single-ended signal is taken from the differential output, terminate both OUT and OUT. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device's total thermal limits should be observed.
IN tPLH OUT
VID OR (VIH - VIL)
0V DIFFERENTIAL
tPHL VOH VOD OR (VOH - VOL)
OUT
VOL
80% +VOD OR +(VOH - VOL) DIFFERENTIAL OUTPUT WAVEFORM OUT - OUT 20% tR -VOD OR -(VOH - VOL) tF
80% 0V DIFFERENTIAL 20%
LVDS Output Termination (MAX9378)
The MAX9378 LVDS outputs are current-steering devices; no output voltage is generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels are dependent upon the value of the termination resistor. The MAX9378 is optimized for point-to-point communication with the 100 termination resistor at the receiver inputs. Termination resistance values may range between 90 and132, depending on the characteristic impedance of the transmission medium.
Figure 3. Differential Input-to-Output Propagation Delay Timing Diagram
Supply Bypassing
Bypass VCC to ground with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
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Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four MAX9377/MAX9378
IN 1 OUT 4 OUT tPCO tPCO RST tDR tSET tPLH
IN IN/4 SEL OUT tSEL
Figure 4. Frequency Divider and Reset Timing Diagram
Figure 5. Frequency Select Delay Timing Diagram
Chip Information
MAX9377 TRANSISTOR COUNT: 614 MAX9378 TRANSISTOR COUNT: 614 PROCESS: Bipolar
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Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
MAX9377/MAX9378
4X S
8
8
INCHES DIM A A1 A2 b MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1
E
H
0.60.1
c D e E H L
1
1
0.60.1
S
D
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
c e b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
1 1
J
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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